European Conference on Circuit Theory and Designextraction , Simulation and Iddq Test

EXTRACTION, SIMULATION AND IDDQ TEST GENERATION FOR EFFICIENT BRIDGING FAULT DETECTION IN DIGITAL VLSI CIRCUITS Tzuhao Chen Ibrahim N. Hajj Department of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois, Urbana, IL 61801, USA i-hajj@uiuc.edu Abstract | In this paper we give an overview of recent work in extraction, simulation, and IDDQ test generation for bridging faults (BFs) in digital VLSI circuits. We then show how these techniques can be applied in a hybrid (logic+IDDQ) testing strategy for e cient BF detection in sequential circuits. In this strategy, logic and IDDQ tests are performed in that order. Realistic BFs are rst extracted from circuit layouts. Then a voltage-based BF simulation is performed on the extracted BFs to lter out those BFs that can be detected by logic testing. IDDQ test generation is then performed targeting the remaining BFs. This hybrid testing strategy shows superior fault coverage with very short IDDQ test sets. In addition, the test generation time for this approach is signi cantly shorter than that a recently proposed approach.